Field of the Invention
The present invention relates to a semiconductor device and a semiconductor module, and in particular, relates to a semiconductor device provided with a high withstand voltage semiconductor element and a semiconductor module provided with the semiconductor device.
Description of the Background Art
In evaluating the electrical characteristics of a semiconductor device (testing subject) mounted in a semiconductor wafer or a semiconductor chip, firstly, the semiconductor device is placed on the surface of a chuck stage of a semiconductor evaluation device. Next, the semiconductor device is fixed on the chuck stage through vacuum suction or the like. Thereafter, a contact probe is made into contact with a predetermined surface electrode of the semiconductor device, and the electrical characteristics are evaluated according to electrical inputs and outputs.
In evaluating the electrical characteristics of a vertical semiconductor device to which a large current is applied in a vertical direction (thickness direction) of the semiconductor device, the surface of the chuck stage is used as the surface electrode. Moreover, in order to apply a large current or a high voltage to the semiconductor device, the contact probe is deployed with a number of pins.
In evaluating the electrical characteristics, it is increasingly demanded that a large current or a high voltage is applied to a semiconductor device, and meanwhile in manufacturing a semiconductor device, it is required to have a lower manufacturing cost, thus, developments have been carried out to miniaturize or reduce each individual semiconductor chip in size so as to increase the number of semiconductor chips that can be disposed on one semiconductor wafer.
In order to miniaturize semiconductor chip while preventing an element forming region (active region) where a power semiconductor element is disposed from being narrowed, an effective approach is to narrow a termination region which surrounds the element forming region. As an example, Japanese Patent Laying-Open No. 2014-204038 discloses a semiconductor device in which the termination region is reduced in footprint.